1. Field of the Invention
This invention relates to a Read Only Memory (ROM) semiconductor device, and more particularly to a structure and method of manufacturing a top floating gate flash EEPROM (Electrically Erasable Programmable Read Only Memory).
2. Description of the Related Art
ROM devices are well known and widely used in the computer technology. In general, a ROM device consists of an array of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) arranged in columns and rows where selected MOSFETS are rendered permanently conductive, or non-conductive, depending on the type of transistor. The ability to set the conductive state of each MOSFET provides a means for storing binary information, and is done typically during a manufacturing process. In a ROM device, this information is non-volatile, i.e., it is maintained even when power is removed from the circuit.
EPROM devices differ from ROMs in their ability to be programmed and erased by a user, after the manufacturing process is complete. They offer advantages such as a small single-cell structure, made of a single MOS transistor with a double-polysilicon gate, and thus high density. Programming is typically accomplished by channel hot-electron injection, outside of the circuit in which the EPROM is used, and erasing by exposure to ultraviolet light, or other means. These somewhat cumbersome techniques explain the popularity of EEPROMs (Electrically Erasable Programmable Read Only Memory), which can be erased and programmed while in-circuit, using Fowler-Nordheim tunneling. However, EEPROMs have a large cell size and require two transistors per cell.
An EEPROM uses a floating gate structure in the MOSFET cell to provide programmability. The floating, or unconnected, gate provides a conductive surface isolated from the source and drain regions of the MOSFET by a thin gate oxide. A second conductive gate, called the control gate, is adjacent to but isolated from the floating gate. The threshold voltage characteristics of the MOSFET cell is controlled by the amount of charge on the floating gate. The amount of charge is set to one of two levels, to indicate whether the cell has been programmed "on" or "off".
The memory cell's state is "read" by applying appropriate voltages to the MOSFET source and drain, and to the control gate, and then sensing the amount of current flow through the transistor. The desired memory cell is selected by choosing the source and drain lines in the column where the cell is located, and applying the control gate voltage to the control gates in the row of the cell being addressed.
The memory cell's programmable state may be erased by removing charge from the floating gate. A fairly recent technology is "Flash" memories, in which the entire array of memory cells, or a significant subset thereof, is erased simultaneously. A conventional Flash memory cell is shown in FIG. 1, in which a control gate 18 has been formed directly over floating gate 16, which electrical charge is applied or removed through tunnel oxide 14 by channel-hot-electron or Fowler-Nordheim tunneling by way of source/drain regions 12, in a substrate 10.
A known problem with the EEPROM is that of "over-erasing", in which positive charge remains on the floating gate after an erase. One solution is the split-gate structure of FIG. 2, which solves the over-erase problem but at the expense of a larger cell size. Source 24 and drain 25 regions are self-aligned in a substrate 23 with the edges of floating-gate 26 and isolation gate 27, respectively. An example is shown in U.S. Pat. No. 4,868,629 (Eitan). Eitan teaches the use of a photoresist pattern to cover part of the floating gate area and the channel region of the "isolation transistor" (which is connected in series with the floating-gate transistor), during source/drain implant.
A problem with this split-gate Flash cell structure is that all program and erase operations take place through the drain, leading to reliability problems and the charge trapping effect. Only the drain junction is underneath the floating gate, and therefore program and erase operations can only be performed through the drain junction. Usually the erase operation causes electron trapping in the tunnel oxide near the drain, which results in less electric field for the program operation, and thus reliability degradation. If the program and erase operations were performed separately, one each through the source and drain areas, the program/erase (endurance) cycles would be improved.